关于FPGA的串口

下面是串口发送模块的程序，为了配合接收模块的波特率这里依然使用了16倍的波特率，在程序中进行处理，但是在编译是出现了如下的错误，认真分析后觉得并没有错误，不知怎么办了，特求助。

编译错误提示如下：

Error (10028): Can't resolve multiple constant drivers for net "n_reg[2]" at tx.v(39)
Error (10029): Constant driver at tx.v(48)
Error (10028): Can't resolve multiple constant drivers for net "n_reg[1]" at tx.v(39)
Error (10028): Can't resolve multiple constant drivers for net "n_reg[0]" at tx.v(39)
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 5 warnings
 Error: Peak virtual memory: 165 megabytes
 Error: Processing ended: Sun Aug 29 14:38:47 2010
 Error: Elapsed time: 00:00:01
 Error: Total CPU time (on all processors): 00:00:01

//下面是源代码

module tx
   #(
   parameter DBIT=8,
   parameter SB_TICK=16
   )
  (
   input wire clk,reset,
   input wire tx_start,s_tick,
   input wire [7:0] din,
   output reg tx_done_tick,
   output wire tx
   );
 //symolic state declaration
 localparam[1:0] idle=2'b00;
 localparam[1:0]  start=2'b01;
 localparam[1:0]  data=2'b10;
 localparam[1:0]  stop=2'b11;
  
  
 //signal declaration
 reg[1:0]state_reg,state_next;
 reg[3:0] s_reg,s_next;
 reg[2:0] n_reg,n_next;
 reg[7:0] b_reg,b_next;
 reg tx_reg,tx_next;
  //body
  //FSMD state&data register
  always@(posedge clk,posedge reset)
    if (reset)
       begin
          state_reg<=idle;
          s_reg<=4'b0000;
          n_reg<=3'b000;
          b_reg<=8'b00000000;
          tx_reg<=1'b1;
        end
    else
      begin
        state_reg<=state_next;
        s_reg<=s_next;
        n_reg<=n_next;
        b_reg<=b_next;
        tx_reg<=tx_next;
      end
  //FSMd next-state logic&functional units
  always@*
    begin
      state_next=state_reg;
      tx_done_tick=1'b0;
      s_next=s_reg;
      n_next=n_reg;
      b_next=b_reg;
      tx_next=tx_reg;
      case(state_reg)
        idle:
          begin
             tx_next=1'b1;
             if (tx_start)
                 begin
                     state_next=start;
                     s_next=0;
                     b_next=din;
                    end
           end
        start:
          begin
             tx_next=1'b0;
             if (s_reg==15)
                 begin
                     state_next=data;
                     s_next=0;
                     n_next=0;
                 end
             else
               s_next=s_reg+1;
         end
       data:
         begin
             tx_next=b_reg[0];
             if(s_tick)
                 if (s_reg==15)
                     begin
                         s_next=0;
                         b_next=b_reg>>1;
                         if(n_reg==(DBIT-1))
                             state_next=stop;
                         else
                            n_reg=n_reg+1;
                     end
                  else
                     s_next=s_reg+1;
          end
        stop:
           begin
             tx_next=1'b1;
             if(s_tick)
                 if(s_reg==(SB_TICK-1))
                     begin
                         state_next=idle;
                         tx_done_tick=1'b1;
                      end
                 else
                   s_next=s_reg+1;
            end
       endcase
   end
  //output
  assign tx=tx_reg;
 
  endmodule
   谢谢！